This invention relates to testing of electronic circuits and, more particularly, to the creation of testing sequences based on a circuit's specifications.
There has always been a need for testing the designs and verifying the operation of electronic systems. In the past, such testing and verifying was devised by the system designers who relied on their knowledge of the intended system behavior and the actual system design.
With advances in Very Large Scale Integration (VLSI), however, this became more difficult. One reason for the difficulty in devising these tests is that there are no internal test points which can be accessed and tested to isolate faults. Another reason is that, most commonly, no repair options are available. Still another reason is that the design philosophy has changed from designs that aim to reduce transistor count, to designs that concentrate on reducing chip "real estate" and input/output interconnection complexities.
The number of active elements created within an integrated circuit currently runs in the hundreds of thousands, and the art is continually striving to increase this number. The masks that must be developed to create these circuits are quite expensive and, therefore, a serious concern in the design of these integrated circuits is that the circuit should perform as intended without undue experimentation. Another concern is that the manufacture of the integrated circuits should not introduce flaws in the circuits, e.g., active elements that are stuck at 1 or stuck at 0. An even more important concern is that manufactured IC's which contain flaws should be detected quickly and easily.
To address these concerns, designers have attempted to mechanize the testing process with equipment similar to that disclosed by U.S. Pat. No. 3,883,801, issued May 13, 1975 to G. C. Hess. In the disclosed equipment, a (vector) signal is applied to a circuit under test and the sequence of output signals from the circuit are combined to produce a single binary word that is compared to a reference binary word characteristic of a properly operating circuit. A test pattern is necessary for such test equipment so designers have also attempted to mechanize the development of testing sequences that would appropriately exercise the manufactured integrated circuits. Creating effective tests for circuits that include hundreds of thousands of active elements is by no means trivial, and developing effective tests that are efficient is even more difficult.
In another aspect of the testing problem, one is sometimes faced with the need to test a circuit or system whose design is not known. For example, in the present burgeoning of the telecommunications field, public data networks with specific access protocols have been built in several countries. These networks can interconnect computers and terminals from different vendors as long as the protocols are adhered to. The protocols defining the interfaces are quite complex, and the equipment designed for communicating via these protocols are likewise complex. Before any equipment is connected to a public network, the protocol implementations must be certified to make sure that they conform to the published standard, but establishing certification tests is difficult because the equipment of different vendors is designed by those vendors, and their designs are not known.
It is an object of this invention to develop an effective method for creating a concise set of input/output sequences for testing complex electronic circuits or systems.
It is another object of this invention to provide a method for creating a concise set of input sequences and expected output sequences based on the functional description of circuits or systems.